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MC100LVE222 3.3 V/5.0 V ECL 1:15 Differential /1//2 Clock Driver
The MC100LVE222 is a low skew 1:15 differential /1//2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be indwependently configured to fanout 1X or 1/2X of the input frequency. The LVE222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs. The device tpd is affected by the quantity of output pairs terminated with a minimum occurring with only one output pair and increasing about 10-20 ps for all output pairs. Relative skew distribution is not affected as more pairs are terminated, but the increased tpd does shift the entire distribution. Unused output pairs should be left unterminated (open) to reduce power and switching noise. The MC100LVE222, as with most ECL devices, can be operated from a positive VCC/VCCO supply in PECL mode. This allows the LVE222 to be used for high performance clock distribution in +3.3 V systems. Operation with >3.8 |(VCC or VCCO-VEE| span will require special thermal handling considerations. Designers can take advantage of the LVE222's performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. All power supply pins must be connected. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D.
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LQFP FA SUFFIX CASE 848D
MC100LVE 222 AWLYYWWG 52 1
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
* * * * * * * * * * * * *
200 ps Part-to-Part Skew 50 ps Output-to-Output Skew Selectable 1x or 1/2x Frequency Outputs ESD Protection: >2 kV HBM, >200 V MM The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC/VCCO = 3.0 V to 5.25 V with VEE = 0 V NECL Mode Operating Range: VCC/VCCO = 0 V with VEE = -3.0 V to -5.25 V Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 2 For Additional Information, refer to Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 684 devices Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
October, 2005- Rev. 11
Publication Order Number: MC100LVE222/D
MC100LVE222
VCCO VCCO VCCO Qc0 Qc0 Qc1 Qc1 Qc2 Qc2 Qc3 Qc3 NC NC
Table 1. PIN DESCRIPTION
PIN FUNCTION ECL Differential Input Clock ECL Differential Input Clock ECL Clock Select ECL Master Reset ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL 1 or 2 Select Reference Voltage Output Positive Supply (VCC = VCCO) Negative Supply No Connect
39 VCCO Qb2 Qb2 Qb1 Qb1 Qb0 Qb0 VCCO Qa1 Qa1 Qa0 Qa0 VCCO 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
29
28
27 26 25 24 23 22 21 Qd0 Qd0 Qd1 Qd1 Qd2 Qd2 Qd3 Qd3 Qd4 Qd4 Qd5 Qd5 VCCO
MC100LVE222
20 19 18 17 16 15 14
CLK0, CLK0 CLK1, CLK1 CLK_Sel MR Qa0:1, Qa0:1 Qb0:2, Qb0:2 Qc0:3, Qc0:3 Qd0:5, Qd0:5 fseln VBB VCC/VCCO VEE
NC
Note: All VCC/VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. All VCC/VCCO pins are internally interconnected.
2
3
4
5
6
7
8
9
10
11
12
13
Table 2. FUNCTION TABLE
Function
MR
CLK0
CLK0
CLK1
CLK1
fsela
fselb
fseld
VCC
fselc
VBB
CLK_Sel
VEE
Input MR CLK_Sel fseln
L Active CLK0 /1
H Reset CLK1 /2
Figure 1. Pinout Assignment (Top View)
MR CLK0 CLK0 CLK1 CLK1 CLK_Sel VBB fsela 3 fselb 4 fselc 6 fseld Qd0:5 Qd0:5 Qc0:3 Qc0:3 Qb0:2 Qb0:2 /1 /2 2 Qa0:1 Qa0:1
Figure 2. Logic Diagram
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MC100LVE222
CLK
RESET
Q
1/2Q
Figure 3. Timing Diagram Table 3. MAXIMUM RATINGS
Symbol VCC/VCCO VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM standard board <2 to 3 sec @ 248C 52 LQFP 52 LQFP 52 LQFP Condition 1 VEE = 0 V VCC or VCCO = 0 V VEE = 0 V VCC or VCCO = 0 V Continuous Surge VI (VCC or VCCO) VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 70 48 TBD 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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MC100LVE222
Table 4. LVPECL DC CHARACTERISTICS VCC or VCCO = 3.3 V; VEE = 0.0 V (Note 1)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current Others CLK0, CLK1 0.5 -300 2215 1470 2135 1490 1.92 Min Typ 122 2295 1605 Max 136 2420 1745 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 25C Typ 122 2345 1595 Max 136 2420 1680 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 85C Typ 125 2345 1595 Max 139 2420 1680 2420 1825 2.04 Unit mA mV mV mV mV V
1.3 1.6
2.9 2.9 150
1.2 1.5
2.9 2.9 150
1.2 1.5
2.9 2.9 150
V V mA mA mA
IIH IIL
0.5 -300
0.5 -300
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC/VCCO. VEE can vary +0.3 V to -1.95 V. Operation with |VCC or VCCO-VEE| w3.8 V span will require special thermal handling considerations. 2. Outputs are terminated through a 50 W resistor to (VCC or VCCO) - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC/VCCO. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
Table 5. LVNECL DC CHARACTERISTICS VCC or VCCO = 0.0 V; VEE = -3.3 V (Note 4)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current Others CLK0, CLK1 0.5 -300 -1085 -1830 -1165 -1810 -1.38 Min Typ 122 -1005 -1695 Max 136 -880 -1555 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 25C Typ 122 -955 -1705 Max 136 -880 -1620 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 85C Typ 125 -955 -1705 Max 139 -880 -1620 -880 -1475 -1.26 Unit mA mV mV mV mV V
-2.0 -1.7
-0.4 -0.4 150
-2.1 -1.8
-0.4 -0.4 150
-2.1 -1.8
-0.4 -0.4 150
V V mA mA mA
IIH IIL
0.5 -300
0.5 -300
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC/VCCO. VEE can vary +0.3 V to -1.95 V. Operation with |VCC or VCCO-VEE| w3.8 V span will require special thermal handling considerations. 5. Outputs are terminated through a 50 W resistor to (VCC or VCCO) - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC/VCCO. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
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MC100LVE222
Table 6. AC CHARACTERISTICS VCC or VCCO = 3.3 V; VEE = 0.0 V or VCC/VCCO = 0.0 V; VEE = -3.3 V (Note 7)
-40C Symbol fmax tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay to Output IN (differential) (Note 8) IN (single-ended) (Note 9) MR Within-Device Skew (Note 10) Part-to-Part Skew (Differential Configuration) Random CLOCK Jitter (RMS) Input Swing (Differential) (Note 11) Output Rise/Fall Time 20%-80% 400 200 < 1.0 1000 600 400 200 Min 1.2 1040 940 1100 Typ > 1.5 1140 1140 1250 1240 1290 1400 50 200 < 1.0 1000 600 400 200 Max Min 1.2 1080 980 1170 25C Typ > 1.5 1180 1180 1320 1280 1330 1470 50 200 < 1.0 1000 600 Max Min 1.2 1120 1020 1220 70C Typ > 1.5 1220 1220 1370 1320 1370 1520 50 200 ps Max Unit GHz ps
tskew
tJITTER VPP tr/tf
ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary +0.3 V to -1.95 V. Operation with |VCC or pVCCO-VEE| w3.8 V span will require special thermal handling considerations. 8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 10. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 11. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output.
Q Driver Device Q
Z = 50 W
D Receiver Device
Z = 50 W 50 W 50 W
D
V TT VTT = (VCC or VCCO) - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
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MC100LVE222
ORDERING INFORMATION
Device MC100LVE222FA MC100LVE222FAR2 MC100LVE222FAG MC100LVE222FAR2G Package LQFP-52 LQFP-52 LQFP-52 (Pb-Free) LQFP-52 (Pb-Free) Shipping 160 Units / Rail 1500 / Tape & Reel 160 Units / Rail 1500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1503 AN1504 AN1560 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020 - - - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Low Voltage ECLinPS SPICE Modeling Kit Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices
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MC100LVE222
PACKAGE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 848D-03 ISSUE D
4X 4X 13 TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
-X- X=L, M, N C L AB AB G
52 1
40 39
3X
VIEW Y -M- B V
PLATING
-L-
VIEW Y F
BASE METAL
B1
13 14 26 27
J
A1 S1 A S
-N-
0.13 (0.005)
ROTATED 90 CLOCKWISE
0.05 (0.002)
C -H- -T-
SEATING PLANE
4X
q2 0.10 (0.004) T
C2
4X
q3 VIEW AA
C1 E VIEW AA Z
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003).
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF
INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF
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EEEE CCC EEEE CCC
M
V1
U
D T L-M
S
N
S
SECTION AB-AB
S
W q1 q
2X R
R1
0.25 (0.010)
GAGE PLANE
K
MC100LVE222
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MC100LVE222/D

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